Electronic devices are becoming increasingly connected with the physical infrastructure around us, forming what is known as the Internet-of-Things (IoT). Such IoT devices imbue intelligence into our physical world and have the potential to transform our cities, with diverse applications like smart home devices, automotive electronics, and intelligent transportation systems being realised.
Edge computing in IoT systems allows data processing and analysis to be performed closer to where the data is created, or on the IoT devices, rather than sending the data to the cloud. This allows better security, privacy, and real-time latency for sensitive applications. However, edge computing is limited by the computing power and battery life of the IoT devices.
To address this issue, Professor Tulika Mitra, whose expertise lies in various aspects of design automation of embedded real-time systems, cyber-physical systems, and IoT, has recently embarked on a five-year research programme called PACE, which is funded by the NRF Competitive Research Programme grant. This effort will create an innovative, reusable, versatile, ultra-low power, software programmable hardware accelerator that achieves a 50x improvement in energy efficiency for edge devices. As an illustration of the benefit of such accelerators, it is hoped that PACE could replace current backpack-scale edge analytics solutions carried by rescue service personnel with tiny wearable edge devices.
Prof Mitra is particularly interested in designing highly efficient universal accelerators that can support different application programs at different points through software-defined re-configurability. Her recent development, the HyCUBE accelerator chip, is a novel Coarse- Grained Reconfigurable Array (CGRA) architecture, offering a good balance between flexibility, power efficiency, and performance. Measurements from the HyCUBE chip show great power efficiency improvement compared to commercial IoT platforms.
The EMPOWER app uses AI to analyse data collected from wearable devices such as smart watches to help users monitor their health-related habits and deliver timely in-app notifications or digital ‘nudges’
Featuring Prof Mitra as one of the four trailblazing female researchers at NUS who pushes frontiers in her research field and takes the lead in STEM
Stitch is a novel processing chip that is low-powered and high-performing across many application domains, enabling the wearable device to perform effectively and independently
Wijerathne, D., Li, Z., Bandara, T. K., & Mitra, T. (2022). PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA. In Proceedings of the 59th ACM/IEEE Design Automation Conference (pp 127–132).
Li, Z., Wu, D., Wijerathne, D., & Mitra, T. (2022, April). LISA: Graph Neural Network based Portable Mapping on Spatial Accelerators. In 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA) (pp. 444-459). IEEE.
Bandara, T. K., Wijerathne, D., Mitra, T., & Peh, L. S. (2022, February). REVAMP: a systematic framework for heterogeneous CGRA realization. In Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (pp. 918- 932).
Wang, S., Pathania, A., & Mitra, T. (2020). Neural network inference on mobile SoCs. IEEE Design & Test, 37 (5), 50-57.
Karunaratne, M., Mohite, A. K., Mitra, T., & Peh, L. S. (2017, June). Hycube: A cgra with reconfigurable single-cycle multi-hop interconnect. In Proceedings of the 54th Annual Design Automation Conference 2017 (pp. 1-6).
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